Data Center: from the Grid to the Chip - IEEE Power Electronics Society

Date: 09/07/2026

Time: 9:00 am

Presenter: Marco Liserre, Arkadeb Sengupta, and Kishan Joshi

Abstract: (Sponsored by TC 7) This IEEE PELS webinar examines next‑generation power conversion architectures for data centers, tracing the complete path from the medium‑voltage (MV) grid down to the chip. Starting from MV interfaces and solid-state transformers (SSTs), the session will address DC and hybrid AC/DC distribution, rack-level architectures, and advanced point-of-load (PoL) solutions. We will compare different PoL approaches—including inductive and capacitive converters, resonant and switched-capacitor topologies, and vertically integrated power stages embedded in packages and substrates—and discuss their impact on efficiency, power density, transient performance, and reliability. Special attention will be given to the implications of AI and accelerated computing (GPUs/TPUs), such as extreme current demands, fast dynamics, and tight voltage regulation, and how these reshape power delivery design criteria. AI and accelerated computing have also a strong impact on the system side. The webinar will analyze the impact of large, power‑dense data centers on the electrical grid, addressing issues such as peak demand, power quality, fault ride-through, and grid congestion. Mitigation measures—including energy storage integration, hybrid AC/DC microgrids, grid-supportive control, and demand-side management—will be discussed, as well as the emerging role of hydrogen (H₂) systems for long-duration storage and backup power. Finally, we will link architecture and technology choices to sustainability, CO₂ footprint, and circular economy principles, covering lifecycle efficiency, materials use, design for repair/reuse, and end-of-life strategies. Participants will gain a system-level perspective on how power electronics innovation can enable efficient, reliable, and sustainable data center infrastructures.

Marco Liserre (S’00–M’02–SM’07–F’13) received his MSc and PhD in Electrical Engineering from the Politecnico di Bari, Italy, in 1998 and 2002. He was an Associate Professor at the same institution before becoming Professor of Reliable Power Electronics at Aalborg University, Denmark, in 2012. Since 2013, he has been a Full Professor and Chair of Power Electronics at Kiel University, Germany. Over his career, he has declined several professorship offers from other institutions. He has authored more than 800 technical publications, including a substantial number of journal papers, as well as one book and more than 10 patents, several developed with industry. His work has received over 65,000 citations. He was recognized as a Highly Cited Researcher in Engineering by Clarivate Web of Science from 2014 to 2021. Many of his former students now hold leading roles in academia and industry worldwide. In 2023, he joined Fraunhofer ISIT part-time where is now Head of Business Unit Power Electronics and Acting Director. He is an active member of several IEEE societies, including IAS, PELS, PES, and IES, and has served them in multiple leadership roles. Within IEEE PELS, he is Vice President for Technical Operations. He has co-chaired numerous international conferences. His honors include 16 major awards, among them the 2018 IEEE-IES Mittelmann Achievement Award and the 2023 IEEE-PELS Middlebrook Achievement Award. In 2023, he was named “Ufficiale” by the President of the Italian Republic. Arkadeb Sengupta (S’16) received the B. Tech. degree from IIT Kharagpur, India, in 2020, and the M. Tech. degree from IISc, Bengaluru, India, in 2022, both in electrical engineering. He has been working towards his Ph.D. degree in electrical engineering with the Chair of Power Electronics, Kiel University, Kiel, Germany, since 2022. His research interests include the design and control of power conversion systems. Mr. Sengupta was a member of scientific staff with Kiel University from October 2022 to March 2026, and remains a guest researcher there. He is currently employed as a senior engineer in the R&D section of a UK-based industry. Mr. Sengupta is a recipient of the 2022 INAE Innovative Student Projects Award and the 2025 ECPE Young Engineer Award. Dr. Kishan Joshi received his M.S. & Ph.D. degrees in electrical engineering from Arizona State University, Tempe, AZ, USA in 2016 & 2020 and his B.E in Electronics & Communication from B.V.B. College of Engineering & Technology, Hubli, India. He is currently working as an Analog Engineering Manager at Intel Corp., Santa Clara, CA on fully integrated voltage regulators. Prior to joining Intel, Kishan has worked at Texas Instruments Inc. Tucson, AZ in the Linear Power group designing Low DropOut regulators from 2019 to 2021. From 2012 to 2014 he was a Digital Circuit Designer at Sankalp Semiconductors Pvt. Ltd., India where he worked on standard cell library design for mixed-signal libraries. His current research interests include integrated vertical power delivery, low-power analog design, supply ripple rejection and power management IC design. He is an Associate Editor at Transactions on Power Electronics as well as a peer reviewer for IEEE Access, TCAS-I & II, SSCL, APEC, ISCAS. He is also the Vice-Chair of IEEE Santa Clara Valley Section for 2025 & 2026. From 2022-2024 he has been serving as the Chair of San Francisco Bay Area Council PELS Chapter. He is currently serving as the Regional Chair for IEEE PELS Region 4-6 overseeing ~40 chapters. He is also a member of the PELS TC-10 on design methodologies and PELS TC-2 on Power Components, Integration and Power ICs. Kishan has served as the Electronic Media Co-Chair for ECCE 2025, Tutorials Committee Co-Chair for ECCE 2026, Track Chair for APEC 2026 in the DC-DC Converter Track.