IEEE PELS Workshop- Interlock times – necessary, useful or not needed at all ?

Invitation to attend and contribute to an IEEE-PELS Workshop

“Interlock times – necessary, useful or not needed at all ?”


The workshop is organized and financially sponsored by IEEE-PELS (Power Electronics Society – TC 1) and will take place on Sunday, September 10, 2017.

Politechnika Warszawska (Warsaw University of Technology)

Centrum Zarządzania Innowacjami i Transferem Technologii (CZIiTT)

Ul. Rektorska 4, 00-614 Warsaw (Poland)

from 10 am until 4 pm, followed by a dinner on 6 pm

The workshop will be on the Sunday before the EPE 2017 – ECCE Europe, which is also to take place in Warsaw (Poland). This enables all participants of the workshop to combine their travel with the travel to EPE 2017 – ECCE Europe. The workshop will not charge any participation fee – the on-site expenses are completely sponsored by TC1 from IEEE-PELS.

You are invited to attend and to contribute to this workshop by your experience

During my industrial activities at Robert BOSCH company I learned to use interlock times between the swithcing off of one power semiconductor in an inverter leg before switching on the opposite one. My opinion always was, that the so-called tail current has to be vanished before switching on the opposite semiconductor. In the following time I taught all my students, that the interlock times are necessary to avoid destruction of the inverter by a so-called shoot through.

Recently we supervised a Master Thesis at Technical University of Munich to find out, how far one can shorten the interlock times (to reduce the non-linearities oft he inverter in the low voltage region). The surprising results of the Master Thesis showed, that it is not necessary to wait until the tail current has vanished - the opposite semiconductor can be switched on during the tail current is still flowing. We even could reduce the interlock time to 0 without destroying the inverter.

In the paper “Multilevel Bipolar High Voltage Pulse Source -Interlock Dead Time Reduction” (published 2003) the author found out the H-bridge works properly when the interlock dead time is set to 1.3µs. He didn’t reduce the delay time further because he could only select from five different values (0µs, 1.3 µs, 2.3 µs, 3.3 µs and 4.3 µs) of the delay time predefined by the gate driver he used. … And the circuit works properly.

I was also surprised to read a contribution from Allen Hefner from 1996 – we all know him. In the paper “IGBT half-bridge shoot-through characterization for model validation” the author conducted a series of experiments that are almost the same as we have done within the Master Thesis at TUM. But the load he used is resistive and the circuit is half-bridge. The collector current suffers a “bump” in the current when one IGBT turns on during the tail current of the other one, but this doesn’t affect the proper working of the circuit. We confirmed this phenomenon on our own experimental circuit with resistive load.

The idea of the workshop is to have an open discussion and exchange of experience. Only a few presentations should break the ice and trigger the open talks. If you are interested in doing one of the introductory presentations (5 to 10 minutes – not more), please give me respective feedback directly on my email – we try plan respectively.

We do not plan to upload papers and/or presentation slides to any type of proceedings. We want to keep the participants free from any pressure to participate and contribute freely. We might produce am article for PELS magazine or similar magazine, but we do not intend to include secrets from any company.

If you want to participate in the workshop, please register on-line via the website using the link ‘IEEE-PELS Workshop 2017 „Interlock Times - …“’.

Expecting your participation with interest

Sebastian Styński, Technical University of Warsaw

Ralph Kennel, Technical University of Munich

Rolando Burgos, Virginia Tech